Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips

Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking. To connect a large number of small chips for building a large scale system, a novel chip stacking method called the staggered stacking is proposed that enables the system to be extended to x and y dimensions, not only to z dimension. For such flexible inter-chip communication, we use Inductive coupling ThruChip Interface (TCI). Here, a novel chip staking layout, and its deadlock-free routing design for the case using multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 6.7% on average compared to that of 2D mesh.

本文言語English
ホスト出版物のタイトルProceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015
出版社Institute of Electrical and Electronics Engineers Inc.
ページ41-48
ページ数8
ISBN(電子版)9781479986699
DOI
出版ステータスPublished - 2015 11月 11
イベント9th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015 - Turin, Italy
継続期間: 2015 9月 232015 9月 25

出版物シリーズ

名前Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015

Other

Other9th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015
国/地域Italy
CityTurin
Period15/9/2315/9/25

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

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