Extension of memory controller equipped with MuCCRA-3-DP: Dynamically reconfigurable processor array

Toru Katagiri, Kazuei Hironaka, Hideharu Amano

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

In order to achieve a high performance on the Dynamically Reconfigurable Processor Array(DRPA), it is necessary to use PEs effectively. However, a prototype DRPA, MuCCRA-3-DP needs to generate read/write addresses for accessing data memories, and counts a number of loops on PEs. Hence, PEs of MuCCRA-3-DP can not be used effectively for actual processing of applications. To solve this problem and improve performance. We extend the memory controller of MuCCRA-3-DP and named it MuCCRA-3-EXMC. PEs of MuCCRA-3-EXMC can be concentrated on executing the actual processing by the extended memory controller performing address generation and loop count. Evaluation results showed that MuCCRA-3-EXMC can improve its performance by 12-23% and reduce its energy consumption by 9-20% without a large increase of its area.

本文言語English
ホスト出版物のタイトルProceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012
ページ826-831
ページ数6
DOI
出版ステータスPublished - 2012 12 14
イベント2012 15th International Conference on Network-Based Information Systems, NBIS 2012 - Melbourne, VIC, Australia
継続期間: 2012 9 262012 9 28

出版物シリーズ

名前Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012

Other

Other2012 15th International Conference on Network-Based Information Systems, NBIS 2012
CountryAustralia
CityMelbourne, VIC
Period12/9/2612/9/28

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Information Systems

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