Si nanostructures for single electron device applications are successfully fabricated using a newly developed anisotropic etching technique. The minimum size of the Si nanostructures is about 10 nm, which is much smaller than the lithography limit. The novel process involves two anisotropic etching steps and one selective oxidation step, and is fully compatible with very large scale integration (VLSI) processes. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) observations indicate that the fabricated nanostructures are very uniform and atomically controlled. This process is promising for the future integration of single electron devices into VLSI chips.
|ジャーナル||Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers|
|号||12 SUPPL. B|
|出版ステータス||Published - 1996 12月|
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