Fast interrupt handling scheme by using interrupt wake-up mechanism

研究成果: Conference contribution

抜粋

In recent years, embedded real-time systems have grown in complexity and are required to be able to handle both periodic and aperiodic tasks. When an external interrupt occurs via an I/O peripheral, the program counter jumps to the corresponding exception vector. This results in large overhead due to context switching. However, embedded real-time systems are required to execute tasks in real-time with high precision. The Responsive Multithreaded Processor (RMTP), a prioritized SMT CPU, consists of eight hardware contexts treated as eight logical processing cores and has various hardware mechanisms for fine-grained real-time processing on the order of 10 μs. One hardware mechanism implemented in RMTP is an interrupt wake-up mechanism that enables interrupt-triggered thread wake ups. When a thread is designated to be an interrupt handling thread, it starts execution one clock cycle after an interrupt occurs. In this paper, we design and implement a software mechanism which reduces the interrupt response time by using this mechanism and demonstrate the effectiveness of our proposed method by RTL simulations. Evaluation results show that our proposed method achieves high real-time performance by reducing the interrupt response time by up to 82% compared to the baseline.

元の言語English
ホスト出版物のタイトルProceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019
出版者Institute of Electrical and Electronics Engineers Inc.
ページ109-114
ページ数6
ISBN(電子版)9781728152684
DOI
出版物ステータスPublished - 2019 11
イベント7th International Symposium on Computing and Networking Workshops, CANDARW 2019 - Nagasaki, Japan
継続期間: 2019 11 262019 11 29

出版物シリーズ

名前Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019

Conference

Conference7th International Symposium on Computing and Networking Workshops, CANDARW 2019
Japan
Nagasaki
期間19/11/2619/11/29

ASJC Scopus subject areas

  • Hardware and Architecture
  • Information Systems
  • Artificial Intelligence
  • Computer Networks and Communications

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  • これを引用

    Wada, R., & Yamasaki, N. (2019). Fast interrupt handling scheme by using interrupt wake-up mechanism. : Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019 (pp. 109-114). [8951642] (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CANDARW.2019.00027