Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors

Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Based on the power consumption analysis of a real Dynamically Reconfigurable Processor Array (DRPA) prototype MuCCRA-3, it appears that the key of power saving is keeping the datapath on the Processing Element (PE) array as possible. Fine Grain Partial Reconfiguration (FGPR) is a simple technique to minimize the change of configuration code in a hardware context switching. In FGPR, a configuration code is divided into several components and only the configuration data for the required components are changed. Evaluation results demonstrate that about 15% of the power consumption is reduced with only 0.7% hardware overhead. The total amount of configuration data and its loading time can be also reduced by 37% in average.

本文言語English
ホスト出版物のタイトルFPL 09
ホスト出版物のサブタイトル19th International Conference on Field Programmable Logic and Applications
ページ530-533
ページ数4
DOI
出版ステータスPublished - 2009 11月 25
イベントFPL 09: 19th International Conference on Field Programmable Logic and Applications - Prague, Czech Republic
継続期間: 2009 8月 312009 9月 2

出版物シリーズ

名前FPL 09: 19th International Conference on Field Programmable Logic and Applications

Other

OtherFPL 09: 19th International Conference on Field Programmable Logic and Applications
国/地域Czech Republic
CityPrague
Period09/8/3109/9/2

ASJC Scopus subject areas

  • 計算理論と計算数学
  • コンピュータ サイエンスの応用

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