Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism

Junichi Sawada, Hiroaki Nishi

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

With the recent growth in the quantity and value of data, data holders have come to realize the importance of being able to utilize information that is otherwise abandoned or concealed. In this situation, they face the difficulty of publishing data without revealing private information. One of the methods used to protect private information when publishing data is privacy-preserving method based on constraints known as k-anonymity and l-diversity. In this paper, we propose a hardware architecture composed of Ternary Content Addressable Memory (TCAM) and a cache mechanism to efficiently reduce the time required for executing the methods. An evaluation proves that an implementation of the proposed architecture on a reconfigurable device performs approximately 10-50 times faster than a RAM-based architecture and up to 60% of the information loss can be eliminated by using the cache mechanism.

本文言語English
ホスト出版物のタイトルProceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
ページ499-502
ページ数4
DOI
出版ステータスPublished - 2012 12 12
イベント22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway
継続期間: 2012 8 292012 8 31

出版物シリーズ

名前Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

Other

Other22nd International Conference on Field Programmable Logic and Applications, FPL 2012
CountryNorway
CityOslo
Period12/8/2912/8/31

ASJC Scopus subject areas

  • Computer Science Applications

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