Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism

Junichi Sawada, Hiroaki Nishi

研究成果: Conference contribution

8 引用 (Scopus)

抄録

With the recent growth in the quantity and value of data, data holders have come to realize the importance of being able to utilize information that is otherwise abandoned or concealed. In this situation, they face the difficulty of publishing data without revealing private information. One of the methods used to protect private information when publishing data is privacy-preserving method based on constraints known as k-anonymity and l-diversity. In this paper, we propose a hardware architecture composed of Ternary Content Addressable Memory (TCAM) and a cache mechanism to efficiently reduce the time required for executing the methods. An evaluation proves that an implementation of the proposed architecture on a reconfigurable device performs approximately 10-50 times faster than a RAM-based architecture and up to 60% of the information loss can be eliminated by using the cache mechanism.

元の言語English
ホスト出版物のタイトルProceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
ページ499-502
ページ数4
DOI
出版物ステータスPublished - 2012
イベント22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway
継続期間: 2012 8 292012 8 31

Other

Other22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Norway
Oslo
期間12/8/2912/8/31

Fingerprint

Associative storage
Hardware
Data privacy
Random access storage

ASJC Scopus subject areas

  • Computer Science Applications

これを引用

Sawada, J., & Nishi, H. (2012). Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. : Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 (pp. 499-502). [6339264] https://doi.org/10.1109/FPL.2012.6339264

Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. / Sawada, Junichi; Nishi, Hiroaki.

Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. p. 499-502 6339264.

研究成果: Conference contribution

Sawada, J & Nishi, H 2012, Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. : Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012., 6339264, pp. 499-502, 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, Oslo, Norway, 12/8/29. https://doi.org/10.1109/FPL.2012.6339264
Sawada J, Nishi H. Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. : Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. p. 499-502. 6339264 https://doi.org/10.1109/FPL.2012.6339264
Sawada, Junichi ; Nishi, Hiroaki. / Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. pp. 499-502
@inproceedings{dd57e5fde12847ba8f07fde1506273dc,
title = "Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism",
abstract = "With the recent growth in the quantity and value of data, data holders have come to realize the importance of being able to utilize information that is otherwise abandoned or concealed. In this situation, they face the difficulty of publishing data without revealing private information. One of the methods used to protect private information when publishing data is privacy-preserving method based on constraints known as k-anonymity and l-diversity. In this paper, we propose a hardware architecture composed of Ternary Content Addressable Memory (TCAM) and a cache mechanism to efficiently reduce the time required for executing the methods. An evaluation proves that an implementation of the proposed architecture on a reconfigurable device performs approximately 10-50 times faster than a RAM-based architecture and up to 60{\%} of the information loss can be eliminated by using the cache mechanism.",
author = "Junichi Sawada and Hiroaki Nishi",
year = "2012",
doi = "10.1109/FPL.2012.6339264",
language = "English",
isbn = "9781467322560",
pages = "499--502",
booktitle = "Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012",

}

TY - GEN

T1 - Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism

AU - Sawada, Junichi

AU - Nishi, Hiroaki

PY - 2012

Y1 - 2012

N2 - With the recent growth in the quantity and value of data, data holders have come to realize the importance of being able to utilize information that is otherwise abandoned or concealed. In this situation, they face the difficulty of publishing data without revealing private information. One of the methods used to protect private information when publishing data is privacy-preserving method based on constraints known as k-anonymity and l-diversity. In this paper, we propose a hardware architecture composed of Ternary Content Addressable Memory (TCAM) and a cache mechanism to efficiently reduce the time required for executing the methods. An evaluation proves that an implementation of the proposed architecture on a reconfigurable device performs approximately 10-50 times faster than a RAM-based architecture and up to 60% of the information loss can be eliminated by using the cache mechanism.

AB - With the recent growth in the quantity and value of data, data holders have come to realize the importance of being able to utilize information that is otherwise abandoned or concealed. In this situation, they face the difficulty of publishing data without revealing private information. One of the methods used to protect private information when publishing data is privacy-preserving method based on constraints known as k-anonymity and l-diversity. In this paper, we propose a hardware architecture composed of Ternary Content Addressable Memory (TCAM) and a cache mechanism to efficiently reduce the time required for executing the methods. An evaluation proves that an implementation of the proposed architecture on a reconfigurable device performs approximately 10-50 times faster than a RAM-based architecture and up to 60% of the information loss can be eliminated by using the cache mechanism.

UR - http://www.scopus.com/inward/record.url?scp=84870720062&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84870720062&partnerID=8YFLogxK

U2 - 10.1109/FPL.2012.6339264

DO - 10.1109/FPL.2012.6339264

M3 - Conference contribution

AN - SCOPUS:84870720062

SN - 9781467322560

SP - 499

EP - 502

BT - Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

ER -