Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

Shimizu Sho, Kihara Taku, Arakawa Yutaka, Yamanaka Naoaki, Shiba Kosuke

研究成果: Paper

抜粋

A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.

元の言語English
DOI
出版物ステータスPublished - 2008 12 1
イベント2008 34th European Conference on Optical Communication, ECOC 2008 - Brussels, Belgium
継続期間: 2008 9 212008 9 25

Other

Other2008 34th European Conference on Optical Communication, ECOC 2008
Belgium
Brussels
期間08/9/2108/9/25

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • これを引用

    Sho, S., Taku, K., Yutaka, A., Naoaki, Y., & Kosuke, S. (2008). Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks. 論文発表場所 2008 34th European Conference on Optical Communication, ECOC 2008, Brussels, Belgium. https://doi.org/10.1109/ECOC.2008.4729415