抄録
This paper presents a software and hardware design of an FPGA-based Blokus Duo solver. We used Embedded system called ZYNQ-7000 All Programmable SoC to implement the solver. By combining hardware with software, efficient acceleration is performed. Our system searches a game tree by using the miniMax algorithm with alpha-beta pruning. The implemented solver works at 75MHz with Xilinx Zynq-7000 AP SoC XC7Z020-CLG484 on the Digilent ZedBoard. It can search states after three moves in most cases.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014 |
| 出版社 | Institute of Electrical and Electronics Engineers Inc. |
| ページ | 358-361 |
| ページ数 | 4 |
| ISBN（電子版） | 9781479962457 |
| DOI | |
| 出版ステータス | Published - 2014 |
| イベント | 13th International Conference on Field-Programmable Technology, FPT 2014 - Shanghai, China 継続期間: 2014 12月 10 → 2014 12月 12 |
Other
| Other | 13th International Conference on Field-Programmable Technology, FPT 2014 |
|---|---|
| 国/地域 | China |
| City | Shanghai |
| Period | 14/12/10 → 14/12/12 |
ASJC Scopus subject areas
- 計算理論と計算数学
- コンピュータ サイエンスの応用