Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture

Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

A contact-less approach that connects chips in vertical dimension has a great potential to customize components in 3-D chip multiprocessors (CMPs), assuming card-style components inserted to a single cartridge communicate each other wirelessly using inductive-coupling technology. To simplify the vertical communication interfaces, static Time Division Multiple Access (TDMA) is used for the vertical broadcast buses, while arbitrary or customized topologies can be used for intra-chip networks. In this paper, we propose the Headfirst sliding routing scheme to overcome the simple static TDMA-based vertical buses. Each vertical bus grants a communication time-slot for different chips at the same time periodically, which means these buses work with different phases. Depending on the current time, packets are routed toward the best vertical bus (elevator) just before the elevator acquires its communication time-slot. Network simulations show that Headfirst sliding routing reduces the communication latency by up to 32.7%, and full-system CMP simulations show that it reduces application execution time by 9.9 %. Synthesis results show that the area and critical path delay overheads are modest.

本文言語English
ホスト出版物のタイトル2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013
DOI
出版ステータスPublished - 2013
イベント2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013 - Tempe, AZ, United States
継続期間: 2013 4 212013 4 24

出版物シリーズ

名前2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013

Other

Other2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013
国/地域United States
CityTempe, AZ
Period13/4/2113/4/24

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

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