High-Bandwidth Low-Latency Approximate Interconnection Networks

Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi

研究成果: Conference contribution

9 引用 (Scopus)

抜粋

Computational applications are subject to various kinds of numerical errors, ranging from deterministic round-off errors to soft errors caused by non-deterministic bit flips, which do not lead to application failure but corrupt application results. Non-deterministic bit flips are typically mitigated in hardware using various error correcting codes (ECC). But in practice, due to performance and cost concerns, these techniques do not guarantee error-free execution. On large-scale computing platforms, soft errors occur with non-negligible probability in RAM and on the CPU, and it has become clear that applications must tolerate them. For some applications, this tolerance is intrinsic as result quality can remain acceptable even in the presence of soft errors (e.g., data analysis applications, multimedia applications). Tolerance can also be built into the application, resolving data corruptions in software during application execution. By contrast, today's optical networks hold on to a rigid error-free standard, which imposes limits on network performance scalability. In this work we propose high-bandwidth, low-latency approximate networks with the following three features:(1) Optical links that exploit multi-level quadrature amplitude modulation (QAM) for achieving high bandwidth, (2) Avoidance of forward error correction (FEC), which makes optical link error-prone but affords lower latency, and(3) The use of symbol mapping coding between bit sequence and QAM to ensure data integrity that is sufficient for practical soft-error-tolerant applications. Discrete-event simulation results for application benchmarks show that approx networks achieve speedups up to 2.94 when compared to conventional networks.

元の言語English
ホスト出版物のタイトルProceedings - 2017 IEEE 23rd Symposium on High Performance Computer Architecture, HPCA 2017
出版者IEEE Computer Society
ページ469-480
ページ数12
ISBN(電子版)9781509049851
DOI
出版物ステータスPublished - 2017 5 5
イベント23rd IEEE Symposium on High Performance Computer Architecture, HPCA 2017 - Austin, United States
継続期間: 2017 2 42017 2 8

Other

Other23rd IEEE Symposium on High Performance Computer Architecture, HPCA 2017
United States
Austin
期間17/2/417/2/8

    フィンガープリント

ASJC Scopus subject areas

  • Hardware and Architecture

これを引用

Fujiki, D., Ishii, K., Fujiwara, I., Matsutani, H., Amano, H., Casanova, H., & Koibuchi, M. (2017). High-Bandwidth Low-Latency Approximate Interconnection Networks. : Proceedings - 2017 IEEE 23rd Symposium on High Performance Computer Architecture, HPCA 2017 (pp. 469-480). [7920848] IEEE Computer Society. https://doi.org/10.1109/HPCA.2017.38