High-speed ATM switch with input and cross-point buffers

Yukihiro Doi, Naoaki Yamanaka

研究成果: Article査読

31 被引用数 (Scopus)

抄録

This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1 Gbit/s.

本文言語English
ページ(範囲)310-314
ページ数5
ジャーナルIEICE Transactions on Communications
E76-B
3
出版ステータスPublished - 1993 3 1
外部発表はい

ASJC Scopus subject areas

  • ソフトウェア
  • コンピュータ ネットワークおよび通信
  • 電子工学および電気工学

フィンガープリント

「High-speed ATM switch with input and cross-point buffers」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル