High-speed decompression architecture of compressed HTTP streams for the internet routers

Hironori Okano, Hayato Yamaki, Hiroaki Nishi

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In recent years, studies of DPI have been carried out actively. HTTP packets, which are a kind of DPI target, include GZIP compressed packets, and multi-streamed GZIP compressed HTTP cannot be analyzed directly on routers. Moreover, wire-rate processing is required to achieve on-router analysis. In this paper, HTTP decompressing architecture on routers supporting 40Gbps network is considered, and three mechanisms, which are parallelized architecture, cache architecture and piggy-back method, were proposed for achieving higher throughput. Hardware cost simulations by using Verilog HDL confirms it can achieve 10Gbps throughput at low circuit costs.

本文言語English
ホスト出版物のタイトル2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016
編集者Jan Haase, Dominik Meyer
出版社Institute of Electrical and Electronics Engineers Inc.
ページ31-36
ページ数6
ISBN(電子版)9781509013593
DOI
出版ステータスPublished - 2016 7 20
イベント2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016 - Hamburg, Germany
継続期間: 2016 5 92016 5 10

出版物シリーズ

名前2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016

Other

Other2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016
国/地域Germany
CityHamburg
Period16/5/916/5/10

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

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