High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme

Tadahiro Kuroda, Tetsuya Fujita, Tetsu Nagamatu, Shinichi Yoshioka, Toshikazu Sei, Kenji Matsuo, Yoichiro Hamura, Toshiaki Mori, Masayuki Murota, Masakazu Kakumu, Takayasu Sakurai

研究成果: Conference contribution

35 引用 (Scopus)

抄録

Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.

元の言語English
ホスト出版物のタイトルProceedings of the Custom Integrated Circuits Conference
出版者IEEE
ページ53-56
ページ数4
出版物ステータスPublished - 1996
外部発表Yes
イベントProceedings of the 1996 IEEE Custom Integrated Circuits Conference - San Diego, CA, USA
継続期間: 1996 5 51996 5 8

Other

OtherProceedings of the 1996 IEEE Custom Integrated Circuits Conference
San Diego, CA, USA
期間96/5/596/5/8

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Threshold voltage
Energy dissipation
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Kuroda, T., Fujita, T., Nagamatu, T., Yoshioka, S., Sei, T., Matsuo, K., ... Sakurai, T. (1996). High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme. : Proceedings of the Custom Integrated Circuits Conference (pp. 53-56). IEEE.

High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme. / Kuroda, Tadahiro; Fujita, Tetsuya; Nagamatu, Tetsu; Yoshioka, Shinichi; Sei, Toshikazu; Matsuo, Kenji; Hamura, Yoichiro; Mori, Toshiaki; Murota, Masayuki; Kakumu, Masakazu; Sakurai, Takayasu.

Proceedings of the Custom Integrated Circuits Conference. IEEE, 1996. p. 53-56.

研究成果: Conference contribution

Kuroda, T, Fujita, T, Nagamatu, T, Yoshioka, S, Sei, T, Matsuo, K, Hamura, Y, Mori, T, Murota, M, Kakumu, M & Sakurai, T 1996, High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme. : Proceedings of the Custom Integrated Circuits Conference. IEEE, pp. 53-56, Proceedings of the 1996 IEEE Custom Integrated Circuits Conference, San Diego, CA, USA, 96/5/5.
Kuroda T, Fujita T, Nagamatu T, Yoshioka S, Sei T, Matsuo K その他. High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme. : Proceedings of the Custom Integrated Circuits Conference. IEEE. 1996. p. 53-56
Kuroda, Tadahiro ; Fujita, Tetsuya ; Nagamatu, Tetsu ; Yoshioka, Shinichi ; Sei, Toshikazu ; Matsuo, Kenji ; Hamura, Yoichiro ; Mori, Toshiaki ; Murota, Masayuki ; Kakumu, Masakazu ; Sakurai, Takayasu. / High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme. Proceedings of the Custom Integrated Circuits Conference. IEEE, 1996. pp. 53-56
@inproceedings{551125c131b64e7e902b6e6b94ce54e3,
title = "High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme",
abstract = "Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50{\%} with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.",
author = "Tadahiro Kuroda and Tetsuya Fujita and Tetsu Nagamatu and Shinichi Yoshioka and Toshikazu Sei and Kenji Matsuo and Yoichiro Hamura and Toshiaki Mori and Masayuki Murota and Masakazu Kakumu and Takayasu Sakurai",
year = "1996",
language = "English",
pages = "53--56",
booktitle = "Proceedings of the Custom Integrated Circuits Conference",
publisher = "IEEE",

}

TY - GEN

T1 - High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme

AU - Kuroda, Tadahiro

AU - Fujita, Tetsuya

AU - Nagamatu, Tetsu

AU - Yoshioka, Shinichi

AU - Sei, Toshikazu

AU - Matsuo, Kenji

AU - Hamura, Yoichiro

AU - Mori, Toshiaki

AU - Murota, Masayuki

AU - Kakumu, Masakazu

AU - Sakurai, Takayasu

PY - 1996

Y1 - 1996

N2 - Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.

AB - Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.

UR - http://www.scopus.com/inward/record.url?scp=0029700814&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029700814&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0029700814

SP - 53

EP - 56

BT - Proceedings of the Custom Integrated Circuits Conference

PB - IEEE

ER -