High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme

Tadahiro Kuroda, Tetsuya Fujita, Tetsu Nagamatu, Shinichi Yoshioka, Toshikazu Sei, Kenji Matsuo, Yoichiro Hamura, Toshiaki Mori, Masayuki Murota, Masakazu Kakumu, Takayasu Sakurai

研究成果: Conference article

35 引用 (Scopus)

抜粋

Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.

元の言語English
ページ(範囲)53-56
ページ数4
ジャーナルProceedings of the Custom Integrated Circuits Conference
出版物ステータスPublished - 1996 1 1
外部発表Yes
イベントProceedings of the 1996 IEEE Custom Integrated Circuits Conference - San Diego, CA, USA
継続期間: 1996 5 51996 5 8

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Kuroda, T., Fujita, T., Nagamatu, T., Yoshioka, S., Sei, T., Matsuo, K., Hamura, Y., Mori, T., Murota, M., Kakumu, M., & Sakurai, T. (1996). High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme. Proceedings of the Custom Integrated Circuits Conference, 53-56.