Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.
|ジャーナル||Proceedings of the Custom Integrated Circuits Conference|
|出版物ステータス||Published - 1996 1 1|
|イベント||Proceedings of the 1996 IEEE Custom Integrated Circuits Conference - San Diego, CA, USA|
継続期間: 1996 5 5 → 1996 5 8
ASJC Scopus subject areas
- Electrical and Electronic Engineering