抄録
Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pull-down transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can be employed together to obtain multiple effects in terms of speed and power.
本文言語 | English |
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ホスト出版物のタイトル | Digital Design and Fabrication |
出版社 | CRC Press |
ページ | 3-1-3-16 |
ISBN(電子版) | 9780849386046 |
ISBN(印刷版) | 9780849386022 |
DOI | |
出版ステータス | Published - 2017 1月 1 |
ASJC Scopus subject areas
- コンピュータ サイエンス(全般)
- 工学(全般)