Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pulldown transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can be employed together to obtain multiple effects in terms of speed and power.
|ホスト出版物のタイトル||The Computer Engineering Handbook|
|出版ステータス||Published - 2001 1月 1|
ASJC Scopus subject areas
- コンピュータ サイエンス（全般）