Highlights of the isscc 2013 processors and high performance digital sessions

Timothy Fischer, Byeong Gyu Nam, Leland Chang, Tadahiro Kuroda, Michiel A.P. Pertijs

研究成果: Review article査読

抄録

The IEEE International Solid-State Circuits Conference (ISSCC) is the foremost global forum for presenting advances in solid-state circuits and systems-on-a-chip. Every year since its first issue, the IEEE JOURNAL OF SOLID-STATE CIRCUITS has highlighted some well-received papers from the most recent ISSCC in special issues. The 1.14 B transistor design includes eight 4-issue out-of-order CPUs, shared 8 MB L3 cache, two-levels of on-chip interconnect, DDR controller, four core supplies, and on-board power management. The paper describes design challenges and methodology used in scaling the design from a 65 nm bulk technology to 32 nm and 28 nm processes. Four highly innovative papers were selected from the Energy Efficient Digital sessions at ISSCC 2013. These papers detail some of the leading-edge advancements in energy-efficient digital circuit techniques.

本文言語English
論文番号6690153
ページ(範囲)4-8
ページ数5
ジャーナルIEEE Journal of Solid-State Circuits
49
1
DOI
出版ステータスPublished - 2014 1月
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「Highlights of the isscc 2013 processors and high performance digital sessions」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル