Simple Serial Synchronized (SSS) Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and permits the bit-serial message combining mechanism. From the theoretical analysis and empirical results, it appears that the influence of the hot spot contention is not catastrophic in the small size SSS-MIN (16×16) when some parallel programs from SPLASH benchmark run. In this situation, the effect of the message combining is small. However, in a large system (256 processors), the pass through ratio improves by 11% when a parallel program with relatively large access ratio (r = 0.4) runs. Since the additional hardware for the message combining is only 20% in the SSS-MIN, the message combining is useful in large systems.
|ジャーナル||IEEE Symposium on Parallel and Distributed Processing - Proceedings|
|出版ステータス||Published - 1996 12月 1|
|イベント||Proceedings of the 1996 8th IEEE Symposium on Parallel and Distributed Processing - New Orleans, LA, USA|
継続期間: 1996 10月 23 → 1996 10月 26
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