Implementation and evaluation of the mechanisms for low latency communication on DIMMnet-2

Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyasiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano

研究成果: Conference contribution

抄録

DIMMnet-2 is a network interface for PC cluster, plugged into a DIMM slot. Connecting network interface into commonly used memory bus reduces the cost of building PC cluster compared with using expensive machines with recent high performance I/O bus like PCIX. Moreover, low latency communication from the host CPU can be achieved. In this paper, implementation of the mechanisms for low latency communication on the DIMMnet-2 prototype board by making the best use of the memory slot is shown. Its latency for 4 Bytes data transfer is only 1.4 μs which is lower than those of InfiniBand and QsNET II on condition those host processes are Intel Xeon.

本文言語English
ホスト出版物のタイトルHigh-Performance Computing - 6th International Symposium, ISHPC 2005 and First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers
出版社Springer Verlag
ページ211-218
ページ数8
ISBN(印刷版)3540777032, 9783540777038
DOI
出版ステータスPublished - 2008
イベント6th International Symposium on High Performance Computing, ISHPC 2005 and 1st International Workshop on Advanced Low Power Systems, ALPS 2006 - Nara, Japan
継続期間: 2005 9 72005 9 9

出版物シリーズ

名前Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
4759 LNCS
ISSN(印刷版)0302-9743
ISSN(電子版)1611-3349

Other

Other6th International Symposium on High Performance Computing, ISHPC 2005 and 1st International Workshop on Advanced Low Power Systems, ALPS 2006
CountryJapan
CityNara
Period05/9/705/9/9

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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