In order to manipulate SHD (super high definition) images, a novel parallel processing unit called HiPIPE (Highly Parallel Image Processing Engine) is developed as a project of NOVI-II. The engine is connected to an SHD image display unit and an image data storage unit. Extremely high computational power is obtained by a multicomputer type parallel processing technique. 128 processing elements are connected by a mesh network. Various image coding schemes are carefully explored from the viewpoint of parallel processing, and the problem of processor connections is examined. A novel load-balancing technique, called 2-dimensional butterfly data shuffling, is developed and implemented. The current version of HiPIPE uses just 128 scaler processing elements and has more than twice the power of a single-processor CRAY-2 for a still SHD image coding task.
|ジャーナル||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版ステータス||Published - 1991 12 1|
|イベント||1991 IEEE International Symposium on Circuits and Systems Part 1 (of 5) - Singapore, Singapore|
継続期間: 1991 6 11 → 1991 6 14
ASJC Scopus subject areas
- Electrical and Electronic Engineering