Implementing and evaluating stream applications on the dynamically reconfigurable processor

Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Tom Awashima

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

Dynamically Recon gurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain recon gurable processor that selects a data path from the on-chip repository of sixteen circuit con gurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the rst prototype chip, and evaluation results are presented. By computing parallelly using the Processing Elements(PEs) and distributed memory modules, DRP-1 out-performed Pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on recon gurable processors and discuss their feasibility in boosting system performance.

本文言語English
ホスト出版物のタイトルProceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004
編集者J. Arnold, K.L. Pocek
ページ328-329
ページ数2
DOI
出版ステータスPublished - 2004 12 1
イベントProceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004 - Napa, CA, United States
継続期間: 2004 4 202004 4 23

出版物シリーズ

名前Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004

Other

OtherProceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004
国/地域United States
CityNapa, CA
Period04/4/2004/4/23

ASJC Scopus subject areas

  • 工学(全般)

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