Influence of sampling jitter on discrete time receiver

Mamiko Inamori, Anas M. Bostamam, Yukitoshi Sanada

    研究成果: Conference contribution

    抄録

    In Software De ned Radio (SDR), implementation of RF front-end and Analog-to-Digital Converter (ADC) is an important issue. One type of new schemes proposed for SDR is Discrete Time Receiver (DTR), which processes analog signal directly. In the DTR architecture, the received signal is sampled at radio frequency (RF) and channel selection and demodulation are carried out in the digital domain. This architecture achieves reduction of o -chip components and enables one-chip receiver. However, in this architecture, the sampling jitter generated from phase noise of phase locked loop (PLL) may deteriorate the performance. In this paper, the phase noise of the PLL is modeled and the in uence of the phase noise to the DTR is analyzed. Moreover, the performance of the DTR is evaluated in terms of modulation schemes and signal bandwidth.

    本文言語English
    ホスト出版物のタイトル2005 IEEE 16th International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC 2005
    ページ2391-2395
    ページ数5
    出版ステータスPublished - 2005 12 1
    イベント2005 IEEE 16th International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC 2005 - Berlin, Germany
    継続期間: 2005 9 112005 9 14

    出版物シリーズ

    名前IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC
    4

    Other

    Other2005 IEEE 16th International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC 2005
    CountryGermany
    CityBerlin
    Period05/9/1105/9/14

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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