Instruction buffer mode for multi-context dynamically reconfigurable processors

Torn Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such contexts without wasting a context memory, we propose anew execution mode called instruction buffer mode in addition to the normal multi-context mode. In this mode, a configuration code from the central configuration memory is stored in the instruction buffer and executed directly. Furthermore, by exploiting a multicast method, a single configuration code loaded to the buffer can be executed by multiple processing elements in a SIMD fashion. We also investigate a mode selection policy based on simple formulas. From the result of implementation and evaluation by using a prototype DRPA called MuCCRA-1, it appears that the total execution time is reduced 12% by using the instruction buffer mode, while 12% of the semiconductor area is increased.

本文言語English
ホスト出版物のタイトルProceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
ページ215-220
ページ数6
DOI
出版ステータスPublished - 2008 11月 3
イベント2008 International Conference on Field Programmable Logic and Applications, FPL - Heidelberg, Germany
継続期間: 2008 9月 82008 9月 10

出版物シリーズ

名前Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2008 International Conference on Field Programmable Logic and Applications, FPL
国/地域Germany
CityHeidelberg
Period08/9/808/9/10

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

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