I/Q mismatch compensation ΔΣ modulator using ternary capacitor rotation technique

Masaki Yonekura, Hiroki Ishikuro

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    This paper presents a new technique to suppress I/Q mismatch and decrease power consumption and chip area. The proposed technique uses two methods for all integrators and DAC in the modulator which are main sources of the mismatch and power. One is proposed ternary capacitor rotation technique to compensate the I/Q mismatch and achieve high image-rejection. The other is amplifier-sharing technique to reduce the number of amplifier and power consumption. The third-order 1bit delta-sigma modulator was designed in 65nm CMOS process, and fabricated test chip achieved an image-rejection ratio (IRR) of higher than 70dB throughout a 1MHz bandwidth. The overall power consumption is 12.7mW including I/Q channels.

    本文言語English
    ホスト出版物のタイトルEuropean Solid-State Circuits Conference
    出版社IEEE Computer Society
    ページ229-232
    ページ数4
    2015-October
    ISBN(印刷版)9781467374705
    DOI
    出版ステータスPublished - 2015 10 30
    イベント41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria
    継続期間: 2015 9 142015 9 18

    Other

    Other41st European Solid-State Circuits Conference, ESSCIRC 2015
    国/地域Austria
    CityGraz
    Period15/9/1415/9/18

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学

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