TY - JOUR
T1 - JUMP-1 router chip
T2 - Proceedings of the 1996 IEEE 15th Annual International Phoenix Conference on Computers and Communications
AU - Nishi, Hiroaki
AU - Nishimura, Katsunobu
AU - Anjo, Ken ichiro
AU - Kudoh, Tomohiro
AU - Amano, Hideharu
PY - 1996/1/1
Y1 - 1996/1/1
N2 - JUMP-1 is currently under development by seven Japanese universities to establish techniques of an efficient distributed shared memory on a massively parallel processor. It provides a coherent cache with the reduced hierarchical bit-map directory scheme to achieve cost effective and high performance management. Messages for coherent cache are transferred through a fat tree on the RDT (Recursive Diagonal Torus) interconnection network. The JUMP-1 router supports versatile functions including multicast and acknowledge combining for the reduced hierarchical bit-map directory scheme.
AB - JUMP-1 is currently under development by seven Japanese universities to establish techniques of an efficient distributed shared memory on a massively parallel processor. It provides a coherent cache with the reduced hierarchical bit-map directory scheme to achieve cost effective and high performance management. Messages for coherent cache are transferred through a fat tree on the RDT (Recursive Diagonal Torus) interconnection network. The JUMP-1 router supports versatile functions including multicast and acknowledge combining for the reduced hierarchical bit-map directory scheme.
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M3 - Conference article
AN - SCOPUS:0029700410
SP - 158
EP - 164
JO - Conference Proceedings - International Phoenix Conference on Computers and Communications
JF - Conference Proceedings - International Phoenix Conference on Computers and Communications
SN - 0896-582X
Y2 - 27 March 1996 through 29 March 1996
ER -