Key-value Store Chip Design for Low Power Consumption

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Low-power embedded systems often require simple but flexible functionality for data management. Key-value store is one of data stores, which provides simple API and is easy to scale-out. We developed a dedicated key-value store core as a low-power embedded storage. In this paper, key-value store chip is fabricated with Renesas SOTB 65-nm process technology. We evalute the real chip in terms of power consumption and operating frequency by tuning VDD and body bias voltage. The chip achieved 11.2mW as power consumption with 0.7V VDD if the target frequency is 40MHz. When data rate is low, the system can reduce power consumption by tuning VDD and body bias voltage.

本文言語English
ホスト出版物のタイトルIEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781728117485
DOI
出版ステータスPublished - 2019 5月 23
イベント22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Yokohama, Japan
継続期間: 2019 4月 172019 4月 19

出版物シリーズ

名前IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings

Conference

Conference22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019
国/地域Japan
CityYokohama
Period19/4/1719/4/19

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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