Layout-conscious random topologies for HPC off-chip interconnects

Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova

研究成果: Conference contribution

30 被引用数 (Scopus)

抄録

As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Random network topologies can be used to achieve low hop counts between nodes and thus low latency. However, random topologies lead to increased aggregate cable length and cable packaging complexity on a machine room floor. In this work we propose two new methods for generating random topologies and their physical layout on a floorplan: randomize links after optimizing the physical layout, or optimize the layout after randomizing links. The first method randomly swaps link endpoints for a given non-random topology for which a good physical layout is known. The resulting topology has the same cable length and cable packaging as the original topology, but achieves lower communication latency. The second method creates a random topology with random links picked so that they will not lead to a long physical cable length, and then solves a constrained optimization problem to compute a physical layout that minimizes aggregate cable length. We quantitatively compare these two methods using both graph analysis and cycle-accurate network simulation, including comparisons with previously proposed random topologies and non-random topologies.

本文言語English
ホスト出版物のタイトル19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013
ページ484-495
ページ数12
DOI
出版ステータスPublished - 2013 7 23
イベント19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013 - Shenzhen, China
継続期間: 2013 2 232013 2 27

出版物シリーズ

名前Proceedings - International Symposium on High-Performance Computer Architecture
ISSN(印刷版)1530-0897

Other

Other19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013
国/地域China
CityShenzhen
Period13/2/2313/2/27

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

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