TY - GEN
T1 - Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks
AU - Kawano, Ryuta
AU - Matsutani, Hiroki
AU - Amano, Hideharu
N1 - Funding Information:
Acknowledgment A part of this work was supported by JSPS KAKENHI Grant Number 20K19788.
Publisher Copyright:
© 2020 IEEE.
Copyright:
Copyright 2021 Elsevier B.V., All rights reserved.
PY - 2020/11
Y1 - 2020/11
N2 - As the scale of supercomputers has increased, the end-to-end network latency has become non-negligible on the performance of parallel applications. For this reason, low-latency network topologies achieving the smallest number of hops among switches are drawing attention. The Order/Degree Problem to find the topology with the smallest diameter has revealed that a topology based on graph symmetry and simulated annealing (SA) is optimal for a wide range of system sizes. Focusing on the characteristics of clustering and symmetry of this graph, we extend the method to guarantee the lower limit of the number of cables in each cabinet. The total cable length and cost can be minimized as well as minimizing the deterioration of communication delay. Compared with the conventional network topologies, the proposed network topology can attain higher performance with the smaller total cable length and cost.
AB - As the scale of supercomputers has increased, the end-to-end network latency has become non-negligible on the performance of parallel applications. For this reason, low-latency network topologies achieving the smallest number of hops among switches are drawing attention. The Order/Degree Problem to find the topology with the smallest diameter has revealed that a topology based on graph symmetry and simulated annealing (SA) is optimal for a wide range of system sizes. Focusing on the characteristics of clustering and symmetry of this graph, we extend the method to guarantee the lower limit of the number of cables in each cabinet. The total cable length and cost can be minimized as well as minimizing the deterioration of communication delay. Compared with the conventional network topologies, the proposed network topology can attain higher performance with the smaller total cable length and cost.
KW - High-Performance Computing
KW - Interconnection Networks
KW - Network Topologies
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U2 - 10.1109/CANDARW51189.2020.00029
DO - 10.1109/CANDARW51189.2020.00029
M3 - Conference contribution
AN - SCOPUS:85102204773
T3 - Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020
SP - 93
EP - 99
BT - Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 8th International Symposium on Computing and Networking Workshops, CANDARW 2020
Y2 - 24 November 2020 through 27 November 2020
ER -