Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks

研究成果: Conference contribution

抄録

As the scale of supercomputers has increased, the end-to-end network latency has become non-negligible on the performance of parallel applications. For this reason, low-latency network topologies achieving the smallest number of hops among switches are drawing attention. The Order/Degree Problem to find the topology with the smallest diameter has revealed that a topology based on graph symmetry and simulated annealing (SA) is optimal for a wide range of system sizes. Focusing on the characteristics of clustering and symmetry of this graph, we extend the method to guarantee the lower limit of the number of cables in each cabinet. The total cable length and cost can be minimized as well as minimizing the deterioration of communication delay. Compared with the conventional network topologies, the proposed network topology can attain higher performance with the smaller total cable length and cost.

本文言語English
ホスト出版物のタイトルProceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020
出版社Institute of Electrical and Electronics Engineers Inc.
ページ93-99
ページ数7
ISBN(電子版)9781728199191
DOI
出版ステータスPublished - 2020 11
イベント8th International Symposium on Computing and Networking Workshops, CANDARW 2020 - Virtual, Naha, Japan
継続期間: 2020 11 242020 11 27

出版物シリーズ

名前Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020

Conference

Conference8th International Symposium on Computing and Networking Workshops, CANDARW 2020
CountryJapan
CityVirtual, Naha
Period20/11/2420/11/27

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Hardware and Architecture
  • Computational Mathematics
  • Control and Optimization

フィンガープリント 「Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル