抄録
Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.
| 本文言語 | English |
|---|---|
| ページ（範囲） | 1021-1028 |
| ページ数 | 8 |
| ジャーナル | IEICE Transactions on Electronics |
| 巻 | E84-C |
| 号 | 8 |
| 出版ステータス | Published - 2001 8月 |
ASJC Scopus subject areas
- 電子材料、光学材料、および磁性材料
- 電子工学および電気工学