Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.
|ジャーナル||IEICE Transactions on Electronics|
|出版ステータス||Published - 2001 8月|
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