Low-Power CMOS Digital Design with Dual Embedded Adaptive Power Supplies

Tadahiro Kuroda, Mototsugu Hamada

研究成果: Article査読

47 被引用数 (Scopus)

抄録

A low-power CMOS design methodology with dual embedded adaptive power supplies is presented. A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in decision of the optimal supply voltages within a restricted design time. An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits. Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design.

本文言語English
ページ(範囲)652-655
ページ数4
ジャーナルIEEE Journal of Solid-State Circuits
35
4
DOI
出版ステータスPublished - 2000 4
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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