Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array

Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

A kind of image processing with a low power Dynamically Reconfigurable Processor Array (DRPA) prototype MuCCRA-3 implemented with 65nm CMOS process will be shown. The measured power is also exhibited during execution, and compared with Xilinx Virtex-5 FPGA using exactly the same environment. The demonstration shows that more than 10 times better power efficient computation is achieved using MuCCRA-3. The application design environment of MuCCRA-3 is also shown.

本文言語English
ホスト出版物のタイトルProceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09
ページ364-367
ページ数4
DOI
出版ステータスPublished - 2009 12月 1
イベント2009 International Conference on Field-Programmable Technology, FPT'09 - Sydney, Australia
継続期間: 2009 12月 92009 12月 11

出版物シリーズ

名前Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Other

Other2009 International Conference on Field-Programmable Technology, FPT'09
国/地域Australia
CitySydney
Period09/12/909/12/11

ASJC Scopus subject areas

  • 計算理論と計算数学
  • ハードウェアとアーキテクチャ
  • ソフトウェア

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