抄録
This paper reviews low-voltage device technologies and circuit design techniques for low-power, high- speed CMOS VLSls. Some of the recent developments, such as employing multiple threshold voltage and controlling threshold voltage through substrate bias in bulk CMOS and Silicon on Insulator (SOl) based technologies, are discussed. Future directions of low-power VLSls are also described.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | Low-Power CMOS Design |
| 出版社 | Wiley-IEEE Press |
| ページ | 61-65 |
| ページ数 | 5 |
| ISBN（電子版） | 9780470545058 |
| ISBN（印刷版） | 9780780334298 |
| DOI | |
| 出版ステータス | Published - 1998 1 1 |
| 外部発表 | はい |
ASJC Scopus subject areas
- Engineering(all)
- Computer Science(all)
- Energy(all)