抄録
Irregular LDPC codes can achieve better error rate performance than regular LDPC codes. However, irregular LDPC codes have higher error floors than regular LDPC codes. The Ordered Statistic Decoding (OSD) algorithm achieves Maximum Likelihood (ML) decoding. The ML decoding is effective to lower error floors. However, temporal estimates obtained by the OSD algorithm satisfy the parity check equation of the LDPC code. The OSD algorithm can not lower error floors due to the temporal estimates satisfying the LDPC parity check equation. We proposed the concatenated code constructed with an inner irregular LDPC code and an outer Cyclic Redundancy Check (CRC). Due to CRC we can detect errors from the codeword estimated by the OSD algorithm. Our proposed LDPC code with the proposed decoding can lower error floors in an AWGN channel. However, in wireless access environments, we can not neglect the effects of the channel. The OSD algorithm needs the ordering of each bit based on the reliability. The Channel State Information (CSI) is used for deciding reliability of each bit In this paper, we evaluate the BLock Error Rate (BLER) of the proposed LDPC code with the proposed decoding in a fast fading channel with and without perfect CSI where 'without perfect CSI' means that only the average of the fading amplitudes is known at the receiver. From the computer simulation, we show that the proposed LDPC code with the proposed decoding can lower error floors than the conventional LDPC code with the OSD algorithm in the fast fading channel with and without perfect CSI.
本文言語 | English |
---|---|
ページ(範囲) | 634-638 |
ページ数 | 5 |
ジャーナル | IEEE Vehicular Technology Conference |
巻 | 61 |
号 | 1 |
出版ステータス | Published - 2005 10月 17 |
外部発表 | はい |
イベント | 2005 IEEE 61st Vehicular Technology Conference -VTC 2005 - Spring Stockholm: Paving the Path for a Wireless Future - Stockholm, Sweden 継続期間: 2005 5月 30 → 2005 6月 1 |
ASJC Scopus subject areas
- コンピュータ サイエンスの応用
- 電子工学および電気工学
- 応用数学