LSI implementation of the simple serial synchronized multistage interconnection network

Takayuki Kamei, Masashi Sasahara, Hideharu Amano

研究成果: Paper査読

1 被引用数 (Scopus)

抄録

Most of traditional multistage interconnection network which are blocking networks and packets are transferred in the store-and-forward manner between switching elements with bit-parallel lines. Since the width of communication paths and transferred manner cause pin-limitation problem and complicated structure, the high density implementation and high speed clock is not utilized. The simple serial synchronized (SSS) piled banyan switching fabrics (PBSF) chip is implemented to solve these problems. This switch used PBSF connection structure which obtain higher bandwidth than crossbar with connecting banyan networks in 3 dimensional direction. SSS style control mechanism is adopted both for high speed operation and solving the pin-limitation problem.

本文言語English
ページ673-674
ページ数2
出版ステータスPublished - 1997 1 1
イベントProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn
継続期間: 1997 1 281997 1 31

Other

OtherProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC
CityChiba, Jpn
Period97/1/2897/1/31

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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