抄録
In a Multistage Interconnection Networks (MINs), a snoop cache technique in bus connected multiprocessors cannot be used, and consistency problems must be solved for providing the cache memory between a processor and the switch. To solve these problems, the MINC (MIN with Cache control mechanism) is proposed. In the MINC, cache coherent messages is separated from the data transfer network, and pushed into an LSI chip called the MINC chip. The coherent control is done based on the directory using the Reduced Hierarchical Bit-map Directory scheme (RHBD).
| 本文言語 | English |
|---|---|
| ページ | 337-338 |
| ページ数 | 2 |
| 出版ステータス | Published - 1998 12月 1 |
| イベント | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn 継続期間: 1998 2月 10 → 1998 2月 13 |
Other
| Other | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) |
|---|---|
| City | Yokohama, Jpn |
| Period | 98/2/10 → 98/2/13 |
ASJC Scopus subject areas
- コンピュータ サイエンスの応用
- コンピュータ グラフィックスおよびコンピュータ支援設計
- 電子工学および電気工学