MINC (Multistage Interconnection Network with Cache control mechanism) chip

Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano

研究成果: Paper査読

2 被引用数 (Scopus)

抄録

In a Multistage Interconnection Networks (MINs), a snoop cache technique in bus connected multiprocessors cannot be used, and consistency problems must be solved for providing the cache memory between a processor and the switch. To solve these problems, the MINC (MIN with Cache control mechanism) is proposed. In the MINC, cache coherent messages is separated from the data transfer network, and pushed into an LSI chip called the MINC chip. The coherent control is done based on the directory using the Reduced Hierarchical Bit-map Directory scheme (RHBD).

本文言語English
ページ337-338
ページ数2
出版ステータスPublished - 1998 12 1
イベントProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn
継続期間: 1998 2 101998 2 13

Other

OtherProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
CityYokohama, Jpn
Period98/2/1098/2/13

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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