Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip link for low-power 3-D system integration

Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda

研究成果: Article

10 引用 (Scopus)

抄録

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.

元の言語English
記事番号5208378
ページ(範囲)1238-1243
ページ数6
ジャーナルIEEE Transactions on Very Large Scale Integration (VLSI) Systems
18
発行部数8
DOI
出版物ステータスPublished - 2010 8

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Communication

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

これを引用

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip link for low-power 3-D system integration. / Niitsu, Kiichi; Kohama, Yoshinori; Sugimori, Yasufumi; Kasuga, Kazutaka; Osada, Kenichi; Irie, Naohiko; Ishikuro, Hiroki; Kuroda, Tadahiro.

:: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 巻 18, 番号 8, 5208378, 08.2010, p. 1238-1243.

研究成果: Article

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