MuCCRA chips: Configurable dynamically-reconfigurable processors

Hideharu Amano, Yohei Hasegawa, Satoshi Tsutsumi, Takuro Nakamura, Takashi Nishimura, Vasutan Tanbunheng, Aepu Parimala, Toru Sano, Masaru Kato

研究成果: Conference contribution

43 被引用数 (Scopus)

抄録

Coarse grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine in System-On-Chips (SoCs). Evaluation results in recent researches revealed that the parameters of optimal processor array structure: granularity, functions, array size, context size and interconnection flexibility, are completely different for each application. That is, DRPAs should be configurable for target SoCs and applications. MuCCRA is a project for developing a DRPA generator which can generate RTL model, testing environment and programming environment for various types of DRPAs just by selecting the specific parameters. Here, two prototype chips MuCCRA-1 and MuCCRA-2 developed in the project are introduced and evaluated. MuCCRA-1 was implemented with Rohm's 0.18um CMOS process mainly for multi-media applications, while MuCCRA-2 with ASPLA's 90nm CMOS process was designed focusing on area optimization used as a cost-effective IP in multi-core SoCs.

本文言語English
ホスト出版物のタイトル2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
ページ384-387
ページ数4
DOI
出版ステータスPublished - 2007 12月 1
イベント2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of
継続期間: 2007 11月 122007 11月 14

出版物シリーズ

名前2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Other

Other2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
国/地域Korea, Republic of
CityJeju
Period07/11/1207/11/14

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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