This paper describes a low-noise and low-power spike neural signal amplifier design that has cutoff frequency compensation between the channels and chips variations. The variation of the frequency characteristics of amplifiers should be minimized among the channels and chips. That is a requirement to do the statistical correlation analysis from a neuroscience point of view. Our design includes the adjustable cutoff frequency using 4 bit variable capacitance. After the compensation the variation of the cutoff frequency was reduced to -0.4 kHz to +0.3 kHz from -1.1 kHz to +3.6 kHz that is the value of before trimming under the condition of the target cutoff frequency is 10 kHz. We designed a multi neural signal amplifier using ROHM 0.18 μm CMOS process. The designed neural amplifier has the capacitive coupled differential input to reject large dc offsets generated at the electrode-tissue interface and to avoid the large common mode noise. To achieve the high energy efficiency with low noise to observe the few tens of μV order spike signal, the MOS transistors in OTA are operated at subthreshold region and combined with low pass filter that consumes less than a hundred nW. The amplifier yielded a midband gain of 37.9 dB and the input-referred noise was measured to be 3.76 μVrms while consuming 4.30 μW with a ±0.9 V power supply. These results corresponding to Noise Efficiency Factor (NEF)=2.23 that are close to the value of the limit using a single differential OTA by CMOS process.
|ジャーナル||IEEJ Transactions on Electronics, Information and Systems|
|出版ステータス||Published - 2015 1 1|
ASJC Scopus subject areas
- Electrical and Electronic Engineering