Multichannel Low-Noise Low-Power Amplifier for Neural Signal Acquisition

Yohei Yasuda, Nobuhiko Nakano

研究成果: Article査読


SUMMARY This paper describes a low-noise and low-power spike neural signal amplifier design that has cut-off frequency compensation between channels and chips. The variation of the frequency characteristics of amplifiers should be minimized among the channels and chips. This is a requirement to perform statistical correlation analysis from a neuroscience-oriented point of view. Our design includes an adjustable cut-off frequency using a 4-bit variable capacitance. After compensation, the variation of the cut-off frequency was reduced to between -0.4 kHz and +0.3 kHz from between -1.1 kHz and +3.6 kHz; that is, the value before trimming under the condition of a target cut-off frequency of 10 kHz. We designed a multineural signal amplifier using the Rohm 0.18 μm CMOS process. The designed neural amplifier has capacitive coupled differential input to reject large dc offsets generated at the electrode-tissue interface and to avoid strong common mode noise. To achieve high energy efficiency with low noise in order to observe spike signals of the order of a few tens of mV, the MOS transistors in the OTA are operated in the subthreshold region and combined with a low-pass filter that consumes less than a hundred nW. The amplifier yielded a midband gain of 37.9 dB and the input-referred noise was measured as 3.76 μVrms with a consumption of 4.30 μW, with a ±0.9 V power supply. These results correspond to a noise efficiency factor (NEF) of 2.23, close to the limit using a single differential OTA prepared by a CMOS process.

ジャーナルElectronics and Communications in Japan
出版ステータスPublished - 2016 5月 1

ASJC Scopus subject areas

  • 信号処理
  • 物理学および天文学(全般)
  • コンピュータ ネットワークおよび通信
  • 電子工学および電気工学
  • 応用数学


「Multichannel Low-Noise Low-Power Amplifier for Neural Signal Acquisition」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。