Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches

Yuta Tokusashi, Hiroki Matsutani

研究成果: Article

5 引用 (Scopus)

抜粋

Key-value store accelerators based on field-programmable gate arrays (FPGAs) have been proposed to achieve higher performance per watt than software-based processing. However, because their cache capacity is strictly limited by DRAMs implemented on FPGA boards, their application domains are also limited. To address this issue, the authors propose a multilevel NoSQL cache architecture that utilizes both FPGA-based hardware cache and in-kernel software cache in a complementary style. This motivates them to explore various design options. Simulation results show that their design reduces the cache miss ratio and improves the throughput compared to the nonhierarchical design.

元の言語English
記事番号8065000
ページ(範囲)44-51
ページ数8
ジャーナルIEEE Micro
37
発行部数5
DOI
出版物ステータスPublished - 2017 9 1

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ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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