Multistage interconnection networks with multiple outlets

Toshihiro Hanawa, Hideharu Amano, Yoshifumi Fujikawa

研究成果: Conference contribution

15 被引用数 (Scopus)

抄録

Multistage Interconnection Networks(MINs) with multiple outlets are networks which can support higher bandwidth than that of nonblocking networks by passing multiple packets to the same destination. A novel MIN topology with multiple outlets called Piled Banyan Switching Fabrics (PBSF) is proposed for the Simple Serial Synchronized (SSS)-MIN used in multiprocessors, and analyzed with other two types of MIN with multiple outlets called Multi-Banyan Switching Fabrics (MBSF) and Tandem Banyan Switching Fabrics (TBSF). The throughput of these MINs is evaluated and compared with both the theoretical model and simulation. The PBSF supports the best throughput and latency used for the SSS-MIN. Although the latency of the TBSF is large, the pass-through ratio is close to 1 if the number of connected banyan networks are more than 4. Therefore, the TBSF is useful for the ATM switching networks in which the relatively large latency is tolerable. The conflict-free access of these MINs is also analyzed, and it appears that rows, column, forward and backward diagonal of the matrix can be accessed without conflict.

本文言語English
ホスト出版物のタイトルProceedings of the 1994 International Conference on Parallel Processing, ICPP 1994
出版社Institute of Electrical and Electronics Engineers Inc.
ページI1-I8
ISBN(印刷版)0849324939, 9780849324932
DOI
出版ステータスPublished - 1994 1月 1
イベント23rd International Conference on Parallel Processing, ICPP 1994 - Raleigh, NC, United States
継続期間: 1994 8月 151994 8月 19

出版物シリーズ

名前Proceedings of the International Conference on Parallel Processing
1
ISSN(印刷版)0190-3918

Other

Other23rd International Conference on Parallel Processing, ICPP 1994
国/地域United States
CityRaleigh, NC
Period94/8/1594/8/19

ASJC Scopus subject areas

  • ソフトウェア
  • 数学 (全般)
  • ハードウェアとアーキテクチャ

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