抜粋
A building block convolutional neural network accelerator consists of a host and multiple accelerator chips which can scale the performance by changing the number of stacked chips. In order to program the host and the accelerators, an integrated programming development environment called NAMACHA is proposed. It includes compilers for convolutional neural network accelerators and a system level simulator including inter-chip communication latency. On the simulator, the total application runs 4390x faster than that of the logic level simulation with 1.27% difference of clock cycle counts.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | Proceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017 |
| 出版者 | The International Society for Computers and Their Applications (ISCA) |
| ページ | 101-106 |
| ページ数 | 6 |
| ISBN（電子版） | 9781943436064 |
| 出版物ステータス | Published - 2017 |
| イベント | 32nd International Conference on Computers and Their Applications, CATA 2017 - Honolulu, United States 継続期間: 2017 3 20 → 2017 3 22 |
Other
| Other | 32nd International Conference on Computers and Their Applications, CATA 2017 |
|---|---|
| 国 | United States |
| 市 | Honolulu |
| 期間 | 17/3/20 → 17/3/22 |
フィンガープリント
ASJC Scopus subject areas
- Computer Science Applications
これを引用
Ohkubo, T., Takata, R., Sakamoto, R., Kondo, M., & Amano, H. (2017). Namacha: A software development environment for a multi-chip convolutional network accelerator. ： Proceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017 (pp. 101-106). The International Society for Computers and Their Applications (ISCA).