抄録
A building block convolutional neural network accelerator consists of a host and multiple accelerator chips which can scale the performance by changing the number of stacked chips. In order to program the host and the accelerators, an integrated programming development environment called NAMACHA is proposed. It includes compilers for convolutional neural network accelerators and a system level simulator including inter-chip communication latency. On the simulator, the total application runs 4390x faster than that of the logic level simulation with 1.27% difference of clock cycle counts.
本文言語 | English |
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ホスト出版物のタイトル | Proceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017 |
出版社 | The International Society for Computers and Their Applications (ISCA) |
ページ | 101-106 |
ページ数 | 6 |
ISBN(電子版) | 9781943436064 |
出版ステータス | Published - 2017 |
イベント | 32nd International Conference on Computers and Their Applications, CATA 2017 - Honolulu, United States 継続期間: 2017 3月 20 → 2017 3月 22 |
Other
Other | 32nd International Conference on Computers and Their Applications, CATA 2017 |
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国/地域 | United States |
City | Honolulu |
Period | 17/3/20 → 17/3/22 |
ASJC Scopus subject areas
- コンピュータ サイエンスの応用