New parallel shortest path searching algorithm based on dynamically reconfigurable processor DAPDNA-2

Hiroyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka, Kosuke Shiba

研究成果: Conference contribution

7 引用 (Scopus)

抄録

This paper proposes a parallel shortest path-searching algorithm and implements it on a newly structured parallel reconfigurable processor, DAPDNA-2 (IPFlex Inc). Routing determines the shortest paths from the source to the ultimate destination through intermediate nodes. In Open Shortest Path First (OSPF), Dijkstra's shortest path algorithm, which is the conventional one, finds the shortest paths from the source on a program counter-based processor. The calculation time for Dijkstra's algorithm is O(N2) when the number of nodes is N. When the network scale is large, calculation time required by Dijkstra's algorithm increases rapidly. It's very difficult to compute Dijkstra's algorithm in parallel because of the need for previous calculation results, so Dijkstra's algorithm is unsuitable for parallel processors. Our proposed scheme finds the shortest paths using a simultaneous multi-path search method. In contrast with Dijkstra's algorithm, several nodes can be determined at one time. Moreover, we partition the network into different groups (network groups) and find the all-node pair's shortest path in each group using a pipeline operation. Networks can be abstracted, and the shortest paths in very large networks can be found easily. The proposed scheme can decrease calculation time from O(N2) to O(N) using a pipeline operation on DAPDNA-2. Our simulations show that the proposed algorithm uses 99.6% less calculation time than Dijkstra's algorithm. The proposed algorithm can be applied to the very large Internet network designs of the future.

元の言語English
ホスト出版物のタイトルIEEE International Conference on Communications
ページ1997-2002
ページ数6
DOI
出版物ステータスPublished - 2007
外部発表Yes
イベント2007 IEEE International Conference on Communications, ICC'07 - Glasgow, Scotland, United Kingdom
継続期間: 2007 6 242007 6 28

Other

Other2007 IEEE International Conference on Communications, ICC'07
United Kingdom
Glasgow, Scotland
期間07/6/2407/6/28

Fingerprint

Pipelines
Internet

ASJC Scopus subject areas

  • Media Technology

これを引用

Ishikawa, H., Shimizu, S., Arakawa, Y., Yamanaka, N., & Shiba, K. (2007). New parallel shortest path searching algorithm based on dynamically reconfigurable processor DAPDNA-2. : IEEE International Conference on Communications (pp. 1997-2002). [4289003] https://doi.org/10.1109/ICC.2007.332

New parallel shortest path searching algorithm based on dynamically reconfigurable processor DAPDNA-2. / Ishikawa, Hiroyuki; Shimizu, Sho; Arakawa, Yutaka; Yamanaka, Naoaki; Shiba, Kosuke.

IEEE International Conference on Communications. 2007. p. 1997-2002 4289003.

研究成果: Conference contribution

Ishikawa, H, Shimizu, S, Arakawa, Y, Yamanaka, N & Shiba, K 2007, New parallel shortest path searching algorithm based on dynamically reconfigurable processor DAPDNA-2. : IEEE International Conference on Communications., 4289003, pp. 1997-2002, 2007 IEEE International Conference on Communications, ICC'07, Glasgow, Scotland, United Kingdom, 07/6/24. https://doi.org/10.1109/ICC.2007.332
Ishikawa H, Shimizu S, Arakawa Y, Yamanaka N, Shiba K. New parallel shortest path searching algorithm based on dynamically reconfigurable processor DAPDNA-2. : IEEE International Conference on Communications. 2007. p. 1997-2002. 4289003 https://doi.org/10.1109/ICC.2007.332
Ishikawa, Hiroyuki ; Shimizu, Sho ; Arakawa, Yutaka ; Yamanaka, Naoaki ; Shiba, Kosuke. / New parallel shortest path searching algorithm based on dynamically reconfigurable processor DAPDNA-2. IEEE International Conference on Communications. 2007. pp. 1997-2002
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