A wireless bus for stacked chips in a package is presented. It uses inductive coupling of metal inductors on the chips. This paper discusses inductive inter-chip signaling, transceiver circuit design, modeling of magnetic field and electric circuits, theory for inductor layout optimization, cross talk analysis in its array arrangement, and cross talk countermeasures. A transceiver is designed and fabricated in 0.35μm CMOS and measured. The maximum data rate is 1.2Gb/s/channel with 45mW from 3.3V in 300μm distance. Cross talk is measured by an embedded voilage detector on the chip, Good agreements are found between the measurements and the theoretical calculations. It is found that cross talk is minimized by arranging channels at intervals of a certain distance. A technique based on Time Division Multiple Access is also proposed to further reduce the cross talk.
|出版ステータス||Published - 2004 12月 1|
|イベント||2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, China|
継続期間: 2004 10月 18 → 2004 10月 21
|Other||2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004|
|Period||04/10/18 → 04/10/21|
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