Non-minimal routing strategy for application-specific Networks-on-Chips

Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano

研究成果: Conference contribution

13 引用 (Scopus)

抄録

We propose a deterministic routing strategy called flee which introduces non-minimal paths in order to distribute traffic with a high degree of communication locality in Networks-on-Chips, In the recent design methodology, target system and its application of the Systems-on-a-Chip are designed in system level description language like System-C, and simulated in the early stage of design. The task distribution is statically decided in this stage, and the amount of traffic between nodes can be analyzed. According to the analysis, a path that transfers a large amount of total data is firstly assigned with a relaxed limitation, thus it is mostly minimal. On the other hand, paths for small amount of total data, are secondly established so as not to disturb previously established paths, thus they are sometimes non-minimal. Simulation results show that the flee routing strategy improves up to 28.6% of throughput against the dimension-order routing on typical stream processing application programs.

元の言語English
ホスト出版物のタイトルProceedings of the International Conference on Parallel Processing Workshops
ページ273-281
ページ数9
2005
DOI
出版物ステータスPublished - 2005
イベントInternational Conference on Parallel Processing Workshops 2005, ICPP 2005 - Oslo, Norway
継続期間: 2005 6 142005 6 17

Other

OtherInternational Conference on Parallel Processing Workshops 2005, ICPP 2005
Norway
Oslo
期間05/6/1405/6/17

Fingerprint

Application programs
Throughput
Communication
Processing
Network-on-chip

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Matsutani, H., Koibuchi, M., Yamada, Y., Jouraku, A., & Amano, H. (2005). Non-minimal routing strategy for application-specific Networks-on-Chips. : Proceedings of the International Conference on Parallel Processing Workshops (巻 2005, pp. 273-281). [1488705] https://doi.org/10.1109/ICPPW.2005.59

Non-minimal routing strategy for application-specific Networks-on-Chips. / Matsutani, Hiroki; Koibuchi, Michihiro; Yamada, Yutaka; Jouraku, Akiya; Amano, Hideharu.

Proceedings of the International Conference on Parallel Processing Workshops. 巻 2005 2005. p. 273-281 1488705.

研究成果: Conference contribution

Matsutani, H, Koibuchi, M, Yamada, Y, Jouraku, A & Amano, H 2005, Non-minimal routing strategy for application-specific Networks-on-Chips. : Proceedings of the International Conference on Parallel Processing Workshops. 巻. 2005, 1488705, pp. 273-281, International Conference on Parallel Processing Workshops 2005, ICPP 2005, Oslo, Norway, 05/6/14. https://doi.org/10.1109/ICPPW.2005.59
Matsutani H, Koibuchi M, Yamada Y, Jouraku A, Amano H. Non-minimal routing strategy for application-specific Networks-on-Chips. : Proceedings of the International Conference on Parallel Processing Workshops. 巻 2005. 2005. p. 273-281. 1488705 https://doi.org/10.1109/ICPPW.2005.59
Matsutani, Hiroki ; Koibuchi, Michihiro ; Yamada, Yutaka ; Jouraku, Akiya ; Amano, Hideharu. / Non-minimal routing strategy for application-specific Networks-on-Chips. Proceedings of the International Conference on Parallel Processing Workshops. 巻 2005 2005. pp. 273-281
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