On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck

Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Technology scaling makes designers face difficulties dealing with wire delay of long global interconnects, especially for high-radix networks. In this context, we propose decentralization of on-chip packet routers. A decentralized router consists of submodules, each of which has particular functionality and they are scattered on a link, thereby long wires are segmented. Our starting point is from a conventional router architecture, and we illustrate four case studies to generalize our proposal. We also propose a new buffer design and how to balance pipelines of a router. A proof-of-concept is shown in 28-nm process technology. Our results demonstrate that the decentralization of an on-chip router enables Link Traversal (LT) stages to be eliminated, and the critical path delay is improved by up to 45% with the reduced area compared with a conventional router. As technology advances, the benefit of the decentralized routers become more substantial in the nano-scale era.

本文言語English
ホスト出版物のタイトルProceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015
編集者Diana Marculescu, Andre Ivanov, Partha Pratim Pande, Jose Flich
出版社Association for Computing Machinery, Inc
ISBN(電子版)9781450333962
DOI
出版ステータスPublished - 2015 9月 28
イベント9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015 - Vancouver, Canada
継続期間: 2015 9月 282015 9月 30

出版物シリーズ

名前Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015

Other

Other9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015
国/地域Canada
CityVancouver
Period15/9/2815/9/30

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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