TY - GEN
T1 - Order/Radix Problem
T2 - 46th International Conference on Parallel Processing, ICPP 2017
AU - Yasudo, Ryota
AU - Koibuchi, Michihiro
AU - Nakano, Koji
AU - Matsutani, Hiroki
AU - Amano, Hideharu
N1 - Funding Information:
This work was partially supported by the JST/CREST program entitled “Research and Development on Unified Environment of Accelerated Computing and Interconnection for Post-Petascale Era” in the research area of “Development of System Software Technologies for post-Peta Scale High Performance Computing”.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/1
Y1 - 2017/9/1
N2 - We introduce a novel graph called a host-switch graph, which consists of host vertices and switch vertices. Using host-switch graphs, we formulate a graph problem called an order/radix problem (ORP) for designing low end-to-end latency interconnection networks. Our focus is on reducing the host-to-host average shortest path length (h-ASPL), since the shortest path length between hosts in a host-switch graph corresponds to the end-to-end latency of a network. We hence define ORP as follows: given order (the number of hosts) and radix (the number of ports per switch), find a host-switch graph with the minimum h-ASPL. We demonstrate that the optimal number of switches can mathematically be predicted. On the basis of the prediction, we carry out a randomized algorithm to find a host-switch graph with the minimum h-ASPL. Interestingly, our solutions include a host-switch graph such that switches have the different number of hosts. We then apply host-switch graphs to interconnection networks and evaluate them practically. As compared with the three conventional interconnection networks (the torus, the dragonfly, and the fat-tree), we demonstrate that our networks provide higher performance while the number of switches can decrease.
AB - We introduce a novel graph called a host-switch graph, which consists of host vertices and switch vertices. Using host-switch graphs, we formulate a graph problem called an order/radix problem (ORP) for designing low end-to-end latency interconnection networks. Our focus is on reducing the host-to-host average shortest path length (h-ASPL), since the shortest path length between hosts in a host-switch graph corresponds to the end-to-end latency of a network. We hence define ORP as follows: given order (the number of hosts) and radix (the number of ports per switch), find a host-switch graph with the minimum h-ASPL. We demonstrate that the optimal number of switches can mathematically be predicted. On the basis of the prediction, we carry out a randomized algorithm to find a host-switch graph with the minimum h-ASPL. Interestingly, our solutions include a host-switch graph such that switches have the different number of hosts. We then apply host-switch graphs to interconnection networks and evaluate them practically. As compared with the three conventional interconnection networks (the torus, the dragonfly, and the fat-tree), we demonstrate that our networks provide higher performance while the number of switches can decrease.
KW - Average shortest path length
KW - Graph theory
KW - Interconnection network
KW - Network topology
KW - Optimization
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UR - http://www.scopus.com/inward/citedby.url?scp=85030642879&partnerID=8YFLogxK
U2 - 10.1109/ICPP.2017.41
DO - 10.1109/ICPP.2017.41
M3 - Conference contribution
AN - SCOPUS:85030642879
T3 - Proceedings of the International Conference on Parallel Processing
SP - 322
EP - 331
BT - Proceedings - 46th International Conference on Parallel Processing, ICPP 2017
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 14 August 2017 through 17 August 2017
ER -