Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

We introduce a novel graph called a host-switch graph, which consists of host vertices and switch vertices. Using host-switch graphs, we formulate a graph problem called an order/radix problem (ORP) for designing low end-to-end latency interconnection networks. Our focus is on reducing the host-to-host average shortest path length (h-ASPL), since the shortest path length between hosts in a host-switch graph corresponds to the end-to-end latency of a network. We hence define ORP as follows: given order (the number of hosts) and radix (the number of ports per switch), find a host-switch graph with the minimum h-ASPL. We demonstrate that the optimal number of switches can mathematically be predicted. On the basis of the prediction, we carry out a randomized algorithm to find a host-switch graph with the minimum h-ASPL. Interestingly, our solutions include a host-switch graph such that switches have the different number of hosts. We then apply host-switch graphs to interconnection networks and evaluate them practically. As compared with the three conventional interconnection networks (the torus, the dragonfly, and the fat-tree), we demonstrate that our networks provide higher performance while the number of switches can decrease.

本文言語English
ホスト出版物のタイトルProceedings - 46th International Conference on Parallel Processing, ICPP 2017
出版社Institute of Electrical and Electronics Engineers Inc.
ページ322-331
ページ数10
ISBN(電子版)9781538610428
DOI
出版ステータスPublished - 2017 9 1
イベント46th International Conference on Parallel Processing, ICPP 2017 - Bristol, United Kingdom
継続期間: 2017 8 142017 8 17

Other

Other46th International Conference on Parallel Processing, ICPP 2017
CountryUnited Kingdom
CityBristol
Period17/8/1417/8/17

ASJC Scopus subject areas

  • Software
  • Mathematics(all)
  • Hardware and Architecture

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