Overview of low-power ULSI circuit techniques

Tadahiro Kuroda, Takayasu Sakurai

研究成果: Chapter

抄録

This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSls now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing: 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static circuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.

本文言語English
ホスト出版物のタイトルHigh-Performance System Design
ホスト出版物のサブタイトルCircuits and Logic
出版社John Wiley and Sons Inc.
ページ198-207
ページ数10
ISBN(電子版)9780470544846
ISBN(印刷版)0780347161, 9780780347168
DOI
出版ステータスPublished - 1999 1 1
外部発表はい

ASJC Scopus subject areas

  • 工学(全般)
  • コンピュータ サイエンス(全般)

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