P-WELL/N-WELL COMPATIBLE CMOS PROCESSING FOR ASIC APPLICATIONS.

Tadahiro Kuroda, Hiroyuki Akiba, Hiroaki Suzuki, Takao Aoki

研究成果: Conference contribution

抄録

This paper describes p-well/n-well compatible CMOS device structure and processing for ASIC applications, together with a design methodology and a scaling scenario. Process optimization has been carried out with careful adjustment of impurity profiles. Equivalent characteristics have been realized in both processes in regard to transistor characteristics, speed performance and latch-up immunity. Scaling philosophy has also been established and its properties are demonstrated.

本文言語English
ホスト出版物のタイトルConference on Solid State Devices and Materials
出版社Business Cent for Academic Soc Japan
ページ57-60
ページ数4
ISBN(印刷版)493081314X
出版ステータスPublished - 1986 12 1
外部発表はい

出版物シリーズ

名前Conference on Solid State Devices and Materials

ASJC Scopus subject areas

  • 工学(全般)

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