This paper describes p-well/n-well compatible CMOS device structure and processing for ASIC applications, together with a design methodology and a scaling scenario. Process optimization has been carried out with careful adjustment of impurity profiles. Equivalent characteristics have been realized in both processes in regard to transistor characteristics, speed performance and latch-up immunity. Scaling philosophy has also been established and its properties are demonstrated.
|ホスト出版物のタイトル||Conference on Solid State Devices and Materials|
|出版社||Business Cent for Academic Soc Japan|
|出版ステータス||Published - 1986 12月 1|
|名前||Conference on Solid State Devices and Materials|
ASJC Scopus subject areas