Parallel responsive task on dependable responsive multithreaded processor II

Hiroyuki Chishiro, Yusuke Hatori, Kohei Osawa, Keigo Mizotani, Nobuyuki Yamasaki

研究成果: Conference contribution

2 引用 (Scopus)

抜粋

Cyber-Physical Systems (CPS) are tight integrations of computational and physical worlds for various kinds of applications. For example, a humanoid robot, which is a typical application of CPS, has required timing constraints, low-latency execution, and parallel processing to achieve fine-grained real-time execution. Therefore low-latency parallel real-time computing is an important factor for CPS. In order to achieve such CPS applications, commercial off-the-shelf systems including processors and operating systems are difficult due to many requirements including such system performance and space constraints, and hence proprietary systems are favored. We had developed Dependable Responsive Multithreaded Processor I (D-RMTP I), which has one Responsive Multithreaded Processing Unit (RMT PU) with an 8-way prioritized Simultaneous Multithreading architecture, for parallel real-time computing. In addition, we have developed a high-end processor of D-RMTP I, called Dependable Responsive Multithreaded Processor II (D-RMTP II). D-RMTP II has two RMT PUs for high throughput and eight Flower cores for I/O processing. Our previous work presented Responsive Task, which is a low-latency real-time task with the interrupt wake-up structure to occupy a hardware thread in D-RMTP I for fine-grained real-time execution. Responsive Task can be executed in dozens of microsecond periods with low-jitter though executing real-time tasks simultaneously. Unfortunately, Responsive Task does not support parallel computing. This paper presents Parallel Responsive Task, which is an extension to Responsive Task for parallel computing on D-RMTP II. Evaluations show that Parallel Responsive Task improves the throughput and achieves fine-grained real-time execution with reasonable overhead.

元の言語English
ホスト出版物のタイトルProceedings - 4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications, CPSNA 2016
出版者Institute of Electrical and Electronics Engineers Inc.
ページ89-94
ページ数6
ISBN(電子版)9781509044030
DOI
出版物ステータスPublished - 2016 12 22
イベント4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications, CPSNA 2016 - Nagoya, Japan
継続期間: 2016 10 62016 10 7

Other

Other4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications, CPSNA 2016
Japan
Nagoya
期間16/10/616/10/7

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Networks and Communications
  • Hardware and Architecture
  • Artificial Intelligence
  • Computer Vision and Pattern Recognition

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  • これを引用

    Chishiro, H., Hatori, Y., Osawa, K., Mizotani, K., & Yamasaki, N. (2016). Parallel responsive task on dependable responsive multithreaded processor II. : Proceedings - 4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications, CPSNA 2016 (pp. 89-94). [7796590] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CPSNA.2016.26