Performance analysis of clearspeed's CSX600 interconnects

Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

ClearSpeed's CSX600 that consists of 96 Processing Elements (PEs) employs a one-dimensional array topology for a simple SIMD processing. To clearly show the performance factors and practical issues of NoCs in an existing modern many-core SIMD system, this paper measures and analyzes NoCs of CSX600 called Swazzle and ClearConnect. Evaluation and analysis results show that the sending and receiving overheads are the major limitation factors to the effective network bandwidth. We found that (1) the number of used PEs, (2) the size of transferred data, and (3) data alignment of a shared memory are three main points to make the best use of bandwidth. In addition, we estimated the best- and worst-case latencies of data transfers in parallel applications.

本文言語English
ホスト出版物のタイトルProceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009
ページ203-210
ページ数8
DOI
出版ステータスPublished - 2009 11月 19
イベント2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009 - Chengdu, Sichuan, China
継続期間: 2009 8月 92009 8月 12

出版物シリーズ

名前Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009

Other

Other2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009
国/地域China
CityChengdu, Sichuan
Period09/8/909/8/12

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • ソフトウェア

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